The present invention is directed toward a new technique for digitization of analog speech or radio signals which is not based on noise shaping but rather on companding (COMpressing the volume of a signal at one point and restoring it through exPANsion at another point) such as companded delta-modulation. The most well-known companded delta-modulation principle is called Continuously Variable-Slope Delta or CVSD modulation, and has been employed in applications where low bit rate delta-modulation was the final coding form in which the speech was desired for transmission or storage.
U.S. Pat. No. 5,241,702 discloses a homodyne receiver in which dc offset from the zero intermediate frequency down converters is removed by the differentiation inherent in the use of delta-modulation conversion. The inherent differentiation can then be removed later by reintegrating the converted results numerically in the digital domain. Furthermore, the possibility of achieving a wide dynamic range is disclosed by using companded delta-modulation conversion having a variable step size.
A variable step size may be achieved through varying the current magnitude delivered by a current source or charge pump which is used by the delta-modulator to increment or decrement the voltage on a capacitor to follow the source. U.S. patent application 08/120,426 which is incorporated herein by reference further discloses that the signal to be converted by delta-modulation can advantageously be applied in series with this principal integrator capacitor, the other end of which is connected to the charge pump and a comparator input. The advantage of this arrangement is that both the comparator input and the charge pump output operate at nearly constant voltages which simplifies their design and improves their performance.
However, practical limitations can arise when attempting to program the current magnitudes of a charge pump over a wide range. The upper current level is limited by the size of the pump transistors used, while the lower limit is limited by leakage current from the large transistors. In addition, mismatch between current levels of the pull-up and pull-down charge pump devices causes an error in the signal conversion which manifests itself as an ascending or descending slope on the reintegrated signal. One method of alleviating the slope problem is described in U.S. patent application No. 08/401,127, entitled "Slope, Drift and Offset Compensation In Zero-IF Receivers", filed Mar. 9, 1995, which estimates the slope and adds a correction term in the reintegration process to compensate it. The correction term may need to be dynamically changed in response to the programming of the charge pump current magnitudes. In another method, digital step size values can be stored and adapted separately to correspond to the charge pump's pull-up and pull-down current levels in order to ensure that the digitally reintegrated signal accurately corresponds to the analog integration of charge performed by the principal integrator capacitor. However, it may be necessary in this method to have a plurality of adapted values corresponding to different charge pump current levels which is a complication. These deficiencies in the prior art can be alleviated by using the improved balanced delta-modulation conversion according to the present invention.